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CPU "anatomy"

a_random_ai
  • 37 months ago

So I know what the basic functions and parts of a CPU are, but I don't necessarily know what all of them do. I know that having more cache is better, but I don't know why. I know that higher clock speeds mean better performance, and architecture affects this, but what exactly is being clocked? How does operating frequency affect performance? When I watched the Crash Course video on CPUs, I got über-confused because I was not familiar with Boolean Algebra and how that plays in to computers. Also when explaining it to me, please don't use over or under complicated terminology (I understand some, but not all).

Comments

  • 37 months ago
  • 2 points

In a more abstract explanation: a CPU takes in instructions (usually x86), which encode something the program wants to do, and the data the program wants to manipulate.

The CPU must execute that instruction, and put the output into the correct register and potentially write back to main memory.

The simplest way to do it is to execute instructions sequentially. If CPUs still did that, they would be executing much less than one instruction per cycle, because it takes multiple CPU cycles to move an instruction through all the necessary logic gates.

The first part of improving IPC (Instructions Per Cycle) is pipelining. Most instructions can be broken up into discrete stages that use different parts of the CPU. So, what you can do is begin instruction n+1 before instruction n has finished executing.

This comes with a problem, though: what if instruction n+1 depends on the result of instruction n? For example:

a = b+c

a = a+d

If you naively just start running that second instruction, you will have a result inconsistent with the programmer's intent, because the first instruction has not yet written back to the register containing a. Because of that, pipelined CPUs have to have extensive checks and/or corrections to make sure they always produce the correct result, much as a sequential CPU would. For example, a pipelined CPU might either delay instruction 2 until 1 has finished writing back, or realize "oh, hey, a = b+c+d, I can just re-route the b+c result into the adder alongside d and write back with the finished result".

The next part is superscalar architecture, where you just start executing more than one instruction per cycle. Again, you need a lot of logic (and thus transistors) to ensure that you always end up with the correct result.

This sort of IPC fun-and-games comes at an exponential cost in logic, and has been one of the primary factors in development of multi-core CPUs. With a multi-core CPU, each core is executing an entirely separate thread of instructions. As such, the burden is not on the hardware to ensure a correct result, the burden is on the software to ensure a correct result. This relieves hardware engineers as much as it drives software developers nuts.

EDIT: Stupid formatting.

  • 37 months ago
  • 1 point

There are registers such as :
Very fast temporary storage for the CPU (Cache)
Program counter (PC)
Accumulator (AC)
Instruction register (IR)
Status flags

Then there is the arithmetic logic unit (ALU) and the control unit.

I have a powerpoint that explains it better that I can send to you, I just need to find it.

[comment deleted]
[comment deleted]
  • 37 months ago
  • 1 point

That was very informative, thank you very much. I'll have to read it a couple of times just to make sure I really get it, but this is super helpful!

[comment deleted]

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